1. Field of the Invention
This invention relates generally to programmable controlling devices, and more particularly, to the internal storage of information in such devices.
2. Description of the Related Art
Computer systems are classically defined as having a processor, memory, and input/output devices. Recent advances in integrated circuit technology have allowed many of the classical computer functions to be integrated onto a single integrated circuit chip. These devices are known by a variety of terms such as microcontrollers, embedded controllers, microcomputers, and the like. However, they share a common characteristic in that they incorporate most classical computer functions on-chip. Because of their high level of integration, microcontrollers are ideal for applications such as automobile engine controllers, refrigerators, cellular telephones, remote controllers, and the like. In order to alleviate the need for external memory to store the operating program, microcontrollers commonly include nonvolatile memory in the form of read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM or E.sub.2 PROM), or onetime programmable ROM (OTPROM). Such a processor is the industry standard 8051 originally designed by Intel shown in FIG. 1.
FIG. 1 shows external RAM 10 which is used for data storage. External ROM 12 is non-volatile memory used to store the operating program for the microcontroller 14 which is made up of microprocessor 16 and peripherals 18. External RAM 10 and external ROM 12 may or may not be on the same chip as microcontroller 14. Microprocessor 16 is composed of processor 17 and internal RAM 26. Processor 17 is made up of control 20, arithmetic logic unit (ALU) 22 and accumulator 24. Control 20 receives the program from external ROM 12, executes the program instructions and controls all signal flow in microprocessor 16. ALU 22 performs arithmetic and logic operations for the microprocessor and provides an output to the accumulator 24. Internal RAM 26 provides the internal processor control registers needed by the control 20 and accumulator 24. These registers include stack pointer 28, program counter 30, and first and second data pointers 32,34, respectively, which are used by control 20 while executing program instructions. GP registers (General Purpose registers) 36 are the registers used in the accumulator 24. Although accumulator 24 physically contains GP registers 36, the registers are shown diagrammatically in internal RAM 26. The special function registers 38 are the registers for peripherals 18 and are physically located there although they are diagrammatically shown in internal RAM 26.
Peripherals 18 provide the pathway and communications from microprocessor 16 to external devices such as a display or keyboard. I/O ports 0,1,2,3 40-46, respectively, are for the input and output of information from microprocessor 16. Timer 2, timer/counter 0, and timer/counter 1 48-52, respectively, may have values that are externally entered. Interrupt controller 54 would normally occur in conjunction with an input from one of the other peripherals. The serial UART 56 is an interface which converts the serial input from an input device such as the keyboard to bytes that may be used by microprocessor 16.
There are three types of storage elements in the microcontroller, state machines 60 in control 20, registers 38a-h in peripherals 40-54, and the internal RAM 26. The registers in peripherals 40-54 are physically located in the peripherals but are shown as the special function registers 38 in internal RAM 26. These registers are loaded under program control by the processor. They set the configuration of the peripherals. The state machines 60 in controller 20 describe the state of the processor at each point in time (i.e. processor context). As described previously, the remainder of the internal RAM 26 besides the special function registers 38 are internal process control registers which supports control 20, ALU 22, and accumulator 24.
In operation, the program is read from external ROM 12 into control 20 where the instructions are executed. State machines 60 keep the status of the processing as each instruction is executed. Stack pointer 28, program counter 30 and data pointers 32 and 34 are used by the controller during execution of the instructions. ALU 16 performs its logic functions and provides an output to accumulator 24 which uses general purpose registers 36. The data in GP registers 36 goes to I/O ports 40-46 and to a display or keyboard. The special function registers 38a-38h determine how the peripherals 18 including the I/O ports are configured.
FIG. 2 shows a simplified diagram of only the memories and processor of any generic microcontroller an example of which was shown in FIG. 1. Typically, it consists of a non-volatile code store 60 made up of ROM (read only memory) that holds the controlling program. Once loaded this store never changes even when the power is removed. An external volatile memory array of RAM, data store 62, is used to store temporary data. Working register stores 64 are internal RAM which hold data being manipulated by processor 66. In addition, the working registers 64 include peripheral registers which hold data characterizing peripherals such as I/O ports. Instructions for the processor 66 are read from the controlling program in code store 60. There may additionally be a micro-code store 68 that holds data that defines the functionality of the processor 66. State machines 70 are volatile memory which maintains the state of the processor 66 at all times.
When a programmable device such as the microcontroller shown in FIG. 2 is used to control equipment, or is a device used to replace logic, it holds its status in internal volatile working registers 64 and state machines 70. It also holds the status of the controlled peripherals (i.e. I/O ports, timers, interrupt controller in FIG. 1) in the volatile working registers 64. The conditions reached by the processor in executing its controlling software are interrelated and relatively unique for an instant in time. This information when held in volatile memories within the device has to be connected to a power source. If power is taken away, all volatile data is lost and a complex procedure is needed to re establish some semblance of the previous state. Though a nonvolatile store is often added to save critical data in the volatile registers and state machines, it can only store a minor sub set of the entire context that the control system is in at any time. This in any case increases the complexity and cost of such devices, in both hardware and software, and limits its use in certain areas.
It is known that a non-volatile memory will preserve data in the memory during a power down. One type of non-volatile memory is a ferromagnetic memory array (FeRAM). It is useful for applications requiring data retention when power is removed from the memory. EEPROMs and FLASH EEPROMs are well known non-volatile memories that compete with ferroelectric memories in some applications.
The non-volatility of a Ferroelectric memory is due to the bistable characteristic of a ferroelectric memory cell. Two types of memory cells are used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell increases density but is less immune to noise and process variations, and requires a voltage reference for determining a stored memory state. The dual capacitor memory cell stores complementary signals allowing differential sampling of the stored information and is stable.
A dual capacitor ferroelectric memory cell in a memory array couples to a BIT and a BITBAR line that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors and two ferroelectric capacitors. A first transistor couples between the BIT line and a first capacitor. A second transistor couples between the BITBAR line and a second capacitor. The first and second capacitors have a common terminal or plate to which a signal is applied for polarizing the capacitor.
In a write operation, the first and second transistors of the dual capacitor ferroelectric memory cell are enabled to couple the capacitors to the complementary logic levels on the BIT line and the BITBAR line corresponding to a logic state to be stored in memory. The common terminal of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell to one of the two logic states.
In a read operation, the first and second transistors of the dual capacitor memory cell are enabled to couple the information stored on the first and second capacitors to the BIT line and the BITBAR line. A differential signal is generated across the BIT line and the BITBAR line by the dual capacitor memory cell. The differential signal is sensed by a sense amplifier, which provides a signal corresponding to the logic level stored in memory.
Such single and dual capacitor memory cells are shown in U.S. pat. No. 5,619,447, hereby incorporated by reference. This reference also shows an array of ferroelectric cells that form an FeRAM.
What is needed is a programmable microcontroller that does not lose its internally stored information during a power down and may be started up without rebooting at exactly the same point as where it shut down that uses simple circuitry and does not need external backup power sources.